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ISVLSI
2006
IEEE
137views VLSI» more  ISVLSI 2006»
14 years 2 months ago
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low ...
T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J....
DSD
2004
IEEE
169views Hardware» more  DSD 2004»
13 years 11 months ago
Shift Invert Coding (SINV) for Low Power VLSI
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transit...
Jayapreetha Natesan, Damu Radhakrishnan
TVLSI
2010
13 years 2 months ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui
DSD
2006
IEEE
107views Hardware» more  DSD 2006»
14 years 2 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
VTC
2007
IEEE
146views Communications» more  VTC 2007»
14 years 2 months ago
Orthogonal STBC in General Nakagami-m Fading Channels: BER Analysis and Optimal Power Allocation
Abstract— We analyze the performance of multiple-input multiple-output (MIMO) systems employing orthogonal space-time block codes (STBC) in general Nakagami-m fading channels wit...
Andreas Müller, Joachim Speidel