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» The Power of the Middle Bit
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CDES
2006
240views Hardware» more  CDES 2006»
13 years 9 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
JCP
2008
324views more  JCP 2008»
13 years 7 months ago
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, A...
INFOCOM
2012
IEEE
11 years 10 months ago
Jointly optimal bit loading, channel pairing and power allocation for multi-channel relaying
Abstract—We aim to enhance the end-to-end rate of a general dual-hop relay network with multiple channels and finite modulation formats, by jointly optimizing channel pairing, p...
Mahdi Hajiaghayi, Min Dong, Ben Liang
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
13 years 11 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...
DSD
2010
IEEE
126views Hardware» more  DSD 2010»
13 years 8 months ago
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod...