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IPPS
2006
IEEE
14 years 3 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
IROS
2006
IEEE
202views Robotics» more  IROS 2006»
14 years 3 months ago
Topological characterization of mobile robot behavior
— We propose to classify the behaviors of a mobile robot thanks to topological methods as an alternative to metric ones. To do so, we adapt an analysis scheme from Physics of non...
Aurélien Hazan, Frédéric Dave...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 3 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
14 years 3 months ago
Silicon neurons that inhibit to synchronize
Abstract—We present a silicon neuron that uses shunting inhibition (conductance-based) with a synaptic rise-time to achieve synchrony. Synaptic rise-time promotes synchrony by de...
John V. Arthur, Kwabena Boahen
LCN
2006
IEEE
14 years 3 months ago
On Access Point Selection in IEEE 802.11 Wireless Local Area Networks
In wireless local area networks often a station can potentially associate with more than one access point. Therefore, a relevant question is which access point to select “bestâ€...
Murad Abusubaih, James Gross, Sven Wiethölter...
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