100 search results - page 15 / 20 » The Sizing Rules Method for Analog Integrated Circuit Design |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
ISQED
2003
IEEE
14 years 24 days ago
2003
IEEE
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...