Sciweavers

100 search results - page 16 / 20
» The Sizing Rules Method for Analog Integrated Circuit Design
Sort
View
WWW
2009
ACM
14 years 8 months ago
A method of analyzing credibility based on LOD control of digital maps
Digital maps are widely used and appear on all types of platforms for integrating content. Users can change display region and scale by panning, zooming in, and zooming out on a d...
Daisuke Kitayama, Ryong Lee, Kazutoshi Sumiya
DAC
2004
ACM
14 years 8 months ago
Profile-guided microarchitectural floorplanning for deep submicron processor design
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
14 years 4 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
14 years 1 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
14 years 25 days ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan