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SAT
2007
Springer
121views Hardware» more  SAT 2007»
14 years 1 months ago
Applying Logic Synthesis for Speeding Up SAT
SAT solvers are often challenged with very hard problems that remain unsolved after hours of CPU time. The research community meets the challenge in two ways: (1) by improving the ...
Niklas Eén, Alan Mishchenko, Niklas Sö...
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
14 years 3 days ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
ICASSP
2010
IEEE
13 years 6 months ago
A hierarchical Bayesian model for frame representation
In many signal processing problems, it may be fruitful to represent the signal under study in a redundant linear decomposition called a frame. If a probabilistic approach is adopt...
Lotfi Chaâri, Jean-Christophe Pesquet, Jean-...
DAC
1996
ACM
13 years 12 months ago
Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation
- The problem of stochastic sequential machines (SSM) synthesis is addressed and its relationship with the constrained sequence generation problem which arises during power estimat...
Diana Marculescu, Radu Marculescu, Massoud Pedram
ICCAD
1994
IEEE
67views Hardware» more  ICCAD 1994»
13 years 12 months ago
The reproducing placement problem with applications
We study a new placement problem: the reproducing placement problem (RPP). In each phase a module (or gate) is decomposed into two (or more) simpler modules. The goal is nd a \go...
Wei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong