Sciweavers

862 search results - page 128 / 173
» The amorphous FPGA architecture
Sort
View
CEE
2004
205views more  CEE 2004»
13 years 10 months ago
64-bit Block ciphers: hardware implementations and comparison analysis
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are u...
Paris Kitsos, Nicolas Sklavos, Michalis D. Galanis...
SIPS
2008
IEEE
14 years 5 months ago
Low-complexity high-speed 4-D TCM decoder
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture f...
Jinjin He, Zhongfeng Wang, Huaping Liu
ASAP
2007
IEEE
122views Hardware» more  ASAP 2007»
14 years 5 months ago
Parallelizing HMMER for Hardware Acceleration on FPGAs
Profile based Hidden Markov Model is a widely used tool in bioinformatics. While being very valuable to biologists, it is extremely compute intensive and suffers from prohibitive...
Steven Derrien, Patrice Quinton
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 3 months ago
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
U. Girola, A. Picciriello, D. Vincenzoni
FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
14 years 2 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele