862 search results - page 41 / 173 » The amorphous FPGA architecture |
156
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GLVLSI
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
186
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FPGA
2009
ACM
15 years 3 months ago
2009
ACM
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
151
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FPGA
2003
ACM
15 years 10 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
143
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CHES
2007
Springer
15 years 11 months ago
2007
Springer
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
138
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FPGA
1998
ACM
15 years 9 months ago
1998
ACM
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...