Sciweavers

862 search results - page 5 / 173
» The amorphous FPGA architecture
Sort
View
FPGA
1997
ACM
142views FPGA» more  FPGA 1997»
13 years 11 months ago
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current a...
Jonathan Rose, Dwight D. Hill
FPGA
2006
ACM
100views FPGA» more  FPGA 2006»
13 years 11 months ago
A generic lookup cache architecture for network processing applications
Abstract-- In this paper, we introduce a novel architecture for constructing caches for lookup operations that are used in a variety of network processing applications. The disting...
Janardhan Singaraju, John A. Chandy
VLSI
2012
Springer
12 years 2 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
FPGA
2000
ACM
145views FPGA» more  FPGA 2000»
13 years 11 months ago
A C compiler for a processor with a reconfigurable functional unit
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that c...
Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerje...
CAMP
2000
IEEE
13 years 11 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada