761 search results - page 140 / 153 » The art of multiprocessor programming |
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing...
PPOPP
2010
ACM
14 years 2 months ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
CODES
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...