35 search results - page 3 / 7 » The associative-skew clock routing problem |
ICCAD
2002
IEEE
14 years 13 days ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
CSREAESA
2010
13 years 5 months ago
2010
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...