This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
We are developing a module-oriented, multiphysics, mixed-fidelity system simulation environment that will enable engineers to rapidly analyze the performance of a system and to o...
David R. Gardner, Joseph P. Castro, Paul N. Demmie...
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
We analyze the complexity of computing pure strategy Nash equilibria (PSNE) in symmetric games with a fixed number of actions. We restrict ourselves to “compact” representati...
Christopher Thomas Ryan, Albert Xin Jiang, Kevin L...