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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 1 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
14 years 1 months ago
Digital statistical analysis using VHDL
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
Manfred Dietrich, Uwe Eichler, Joachim Haase
HICSS
2002
IEEE
128views Biometrics» more  HICSS 2002»
14 years 1 months ago
Developing a Flexible System-Modeling Environment for Engineers
We are developing a module-oriented, multiphysics, mixed-fidelity system simulation environment that will enable engineers to rapidly analyze the performance of a system and to o...
David R. Gardner, Joseph P. Castro, Paul N. Demmie...
ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
14 years 1 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
SIGECOM
2010
ACM
184views ECommerce» more  SIGECOM 2010»
14 years 1 months ago
Computing pure strategy nash equilibria in compact symmetric games
We analyze the complexity of computing pure strategy Nash equilibria (PSNE) in symmetric games with a fixed number of actions. We restrict ourselves to “compact” representati...
Christopher Thomas Ryan, Albert Xin Jiang, Kevin L...