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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
14 years 26 days ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
DAC
1997
ACM
14 years 24 days ago
A C-Based RTL Design Verification Methodology for Complex Microprocessor
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon ...
ICCAD
1996
IEEE
141views Hardware» more  ICCAD 1996»
14 years 23 days ago
An observability-based code coverage metric for functional simulation
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
EDCC
1994
Springer
14 years 21 days ago
RIFLE: A General Purpose Pin-level Fault Injector
This paper discusses the problems of pin-level fault injection for dependability validation and presents the architecture of a pin-level fault injector called RIFLE. This system ca...
Henrique Madeira, Mário Zenha Rela, Francis...
CEC
2007
IEEE
13 years 10 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...