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CODES
2005
IEEE
14 years 1 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 29 days ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
ICCAD
2007
IEEE
119views Hardware» more  ICCAD 2007»
13 years 9 months ago
IntSim: A CAD tool for optimization of multilevel interconnect networks
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffre...
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 9 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
BMCBI
2006
114views more  BMCBI 2006»
13 years 7 months ago
Epigenetic acquisition of inducibility of type III cytotoxicity in P. aeruginosa
Background: Pseudomonas aeruginosa, an opportunistic pathogen, is often encountered in chronic lung diseases such as cystic fibrosis or chronic obstructive pneumonia, as well as a...
Didier Filopon, Annabelle Mérieau, Gilles B...