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» The behavior of resistive circuits
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ETS
2009
IEEE
98views Hardware» more  ETS 2009»
13 years 6 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
VLSI
2010
Springer
13 years 3 months ago
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation...
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, S...
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
14 years 5 days ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 5 months ago
From molecular interactions to gates: a systematic approach
The continuous minituarization of integrated circuits may reach atomic scales in a couple of decades. Some researchers have already built simple computation engines by manipulatin...
Josep Carmona, Jordi Cortadella, Yousuke Takada, F...
ICCAD
2002
IEEE
129views Hardware» more  ICCAD 2002»
14 years 5 months ago
Transmission line design of clock trees
We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations pr...
Rafael Escovar, Roberto Suaya