55 search results - page 5 / 11 » The design and implementation of a low-latency on-chip netwo... |
ISCAS
2005
IEEE
14 years 3 months ago
2005
IEEE
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
ICPP
2000
IEEE
14 years 2 months ago
2000
IEEE
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
SLIP
2006
ACM
14 years 3 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
ANCS
2007
ACM
14 years 1 months ago
2007
ACM
Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...