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» The design of a high performance low power microprocessor
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CODES
2007
IEEE
14 years 26 days ago
Energy efficient co-scheduling in dynamically reconfigurable systems
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu
GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...
ASYNC
2003
IEEE
119views Hardware» more  ASYNC 2003»
14 years 2 months ago
Asynchronous DRAM Design and Synthesis
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
Virantha N. Ekanayake, Rajit Manohar
SECON
2008
IEEE
14 years 3 months ago
Adaptive Radio Modes in Sensor Networks: How Deep to Sleep?
—Energy-efficient performance is a central challenge in sensor network deployments, and the radio is a major contributor to overall energy node consumption. Current energyeffic...
Raja Jurdak, Antonio G. Ruzzelli, Gregory M. P. O'...
TPDS
2010
94views more  TPDS 2010»
13 years 7 months ago
MIMO Power Control for High-Density Servers in an Enclosure
—Power control is becoming a key challenge for effectively operating a modern data center. In addition to reducing operating costs, precisely controlling power consumption is an ...
Xiaorui Wang, Ming Chen, Xing Fu