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» The design of a high performance low power microprocessor
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DAC
2005
ACM
14 years 8 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 11 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
DCC
2000
IEEE
13 years 12 months ago
Arithmetic Coding for Low Power Embedded System Design
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
Haris Lekatsas, Wayne Wolf, Jörg Henkel
IJCSA
2008
100views more  IJCSA 2008»
13 years 7 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
14 years 24 days ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak