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» The design of a high performance low power microprocessor
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ISPASS
2006
IEEE
14 years 2 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
ISCAS
2005
IEEE
141views Hardware» more  ISCAS 2005»
14 years 2 months ago
A low voltage CMOS multiplier for high frequency equalization
- This paper describes the design of a low power
Justin P. Abbott, Calvin Plett, John W. M. Rogers
IPPS
2006
IEEE
14 years 2 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
AINA
2007
IEEE
14 years 3 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
ISCA
2005
IEEE
172views Hardware» more  ISCA 2005»
14 years 2 months ago
An Ultra Low Power System Architecture for Sensor Network Applications
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networ...
Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu...