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» The design of a high performance low power microprocessor
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DATE
2003
IEEE
86views Hardware» more  DATE 2003»
14 years 2 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
DAC
2005
ACM
13 years 10 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 5 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
CORR
2010
Springer
196views Education» more  CORR 2010»
13 years 9 months ago
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computin...
H. G. Rangaraju, U. Venugopal, K. N. Muralidhara, ...
ICIP
2001
IEEE
14 years 10 months ago
Motion estimation for low power video devices
We propose a block motion estimation (ME) algorithm that meets high quality requirements and allows for cost efficient VLSI realizations. It relies on a set of rules common to all...
Christophe De Vleeschouwer, Tord Nilsson