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ISCAS
2008
IEEE
265views Hardware» more  ISCAS 2008»
14 years 3 months ago
Dynamic voltage and frequency scaling circuits with two supply voltages
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
Wayne H. Cheng, Bevan M. Baas
ARITH
2003
IEEE
14 years 2 months ago
High-Performance Left-to-Right Array Multiplier Design
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
Zhijun Huang, Milos D. Ercegovac
ISLPED
2003
ACM
152views Hardware» more  ISLPED 2003»
14 years 2 months ago
An MTCMOS design methodology and its application to mobile computing
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are use...
Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae P...
DAC
2009
ACM
14 years 9 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
IISWC
2006
IEEE
14 years 2 months ago
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks
Many embedded real world applications are intellectual property, and vendors hesitate to share these proprietary applications with computer architects and designers. This poses a ...
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., L...