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» The design of a high performance low power microprocessor
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ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
14 years 1 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 2 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 5 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 3 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
AGENTS
1997
Springer
14 years 1 months ago
High-Level Planning and Low-Level Execution: Towards a Complete Robotic Agent
We have been developing Rogue, an architecture that integrates high-level planning with a low-level executing robotic agent. Rogue is designed as the oce gofer task planner for X...
Karen Zita Haigh, Manuela M. Veloso