1994 search results - page 89 / 399 » The design of a high performance low power microprocessor |
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
ISCA
2007
IEEE
14 years 3 months ago
2007
IEEE
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...