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» The design of a high performance low power microprocessor
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DATE
2006
IEEE
95views Hardware» more  DATE 2006»
14 years 3 months ago
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault d...
Paolo Bernardi, Ernesto Sánchez, Massimilia...
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
14 years 2 months ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
PVLDB
2010
164views more  PVLDB 2010»
13 years 7 months ago
FlashStore: High Throughput Persistent Key-Value Store
We present FlashStore, a high throughput persistent keyvalue store, that uses flash memory as a non-volatile cache between RAM and hard disk. FlashStore is designed to store the ...
Biplob Debnath, Sudipta Sengupta, Jin Li
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 2 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
DAC
2005
ACM
14 years 10 months ago
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
Yan Lin, Lei He