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» The design of a low energy FPGA
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DAC
2007
ACM
14 years 9 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 5 months ago
Design and Implementation of Software Objects in Hardware
This paper proposes a novel approach to implement software object in hardware. Data-Memory mapping schemes are investigated and four hardware object design schemes are proposed an...
Fu-Chiung Cheng, Hung-Chi Wu
CASES
2007
ACM
14 years 14 days ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
EENERGY
2010
13 years 9 months ago
A simple analytical model for the energy-efficient activation of access points in dense WLANs
Energy efficient networks are becoming a hot research topic, and the networking community is increasingly devoting its attention to the identification of approaches to save energy...
Marco Ajmone Marsan, Luca Chiaraviglio, Delia Ciul...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 8 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood