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» The design of a low energy FPGA
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ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 8 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
DELTA
2010
IEEE
14 years 1 months ago
Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor
Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of...
Hans G. Kerkhoff, Xiao Zhang
VLSI
2007
Springer
14 years 2 months ago
An efficient H.264 intra frame coder system design
In this paper, we present an efficient H.264 / MPEG4 Part 10 Intra Frame Coder System. The system achieves real-time performance for portable applications with low hardware cost, ...
Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 2 months ago
Compact hardware design of Whirlpool hashing core
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
Timo Alho, Panu Hämäläinen, Marko H...
CF
2011
ACM
12 years 8 months ago
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
Bojan Maric, Jaume Abella, Francisco J. Cazorla, M...