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» The design of a low energy FPGA
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IJCSS
2007
133views more  IJCSS 2007»
13 years 9 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
14 years 1 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
DATE
2008
IEEE
97views Hardware» more  DATE 2008»
13 years 11 months ago
Energy Efficient and High Speed On-Chip Ternary Bus
We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary codin...
Chunjie Duan, Sunil P. Khatri
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
14 years 4 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
CORR
2010
Springer
177views Education» more  CORR 2010»
13 years 7 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai