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» The design of a low energy FPGA
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ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 4 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
ICOIN
2007
Springer
14 years 1 months ago
Collision-Free Downlink Scheduling in the IEEE 802.15.4 Network
Abstract. IEEE 802.15.4 is the Low-Rate Wireless Personal Area Network (LR-WPAN) standard that is suitable for wireless sensor networks and wireless home networks among others. The...
Sangki Yun, Hyogon Kim
ICDCS
2007
IEEE
14 years 1 months ago
Protocol Design and Optimization for Delay/Fault-Tolerant Mobile Sensor Networks
While extensive studies have been carried out in the past several years for many sensor applications, they cannot be applied to the network with extremely low and intermittent con...
Yu Wang, Hongyi Wu, Feng Lin, Nian-Feng Tzeng
GLOBECOM
2006
IEEE
14 years 1 months ago
Implementation of a Coded Modulation for Deep Space Optical Communications
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
Michael K. Cheng, Bruce E. Moision, Jon Hamkins, M...
DAC
2009
ACM
14 years 8 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong