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» The design of a low energy FPGA
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DAC
2003
ACM
14 years 8 months ago
A low-energy chip-set for wireless intercom
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the pr...
M. Josie Ammer, Michael Sheets, Tufan C. Karalar, ...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 7 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
INFOCOM
2008
IEEE
14 years 1 months ago
On the Construction of a Maximum-Lifetime Data Gathering Tree in Sensor Networks: NP-Completeness and Approximation Algorithm
Abstract—Energy efficiency is critical for wireless sensor networks. The data gathering process must be carefully designed to conserve energy and extend the network lifetime. Fo...
Yan Wu, Sonia Fahmy, Ness B. Shroff
GLVLSI
2006
IEEE
155views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Dynamic voltage scaling for multitasking real-time systems with uncertain execution time
Dynamic voltage scaling (DVS) for real-time systems has been extensively studied to save energy. Previous studies consider the probabilistic distributions of tasks’ execution ti...
Changjiu Xian, Yung-Hsiang Lu
TON
2010
171views more  TON 2010»
13 years 2 months ago
Constructing Maximum-Lifetime Data-Gathering Forests in Sensor Networks
Abstract--Energy efficiency is critical for wireless sensor networks. The data-gathering process must be carefully designed to conserve energy and extend network lifetime. For appl...
Yan Wu, Zhoujia Mao, Sonia Fahmy, Ness B. Shroff