Sciweavers

517 search results - page 67 / 104
» The design of a low energy FPGA
Sort
View
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
14 years 1 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...
ISCA
2009
IEEE
192views Hardware» more  ISCA 2009»
14 years 2 months ago
A case for bufferless routing in on-chip networks
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
Thomas Moscibroda, Onur Mutlu
MOBICOM
2012
ACM
11 years 9 months ago
RadioJockey: mining program execution to optimize cellular radio usage
Many networked applications that run in the background on a mobile device incur significant energy drains when using the cellular radio interface for communication. This is mainl...
Pavan K. Athivarapu, Ranjita Bhagwan, Saikat Guha,...
GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
DAC
2006
ACM
14 years 8 months ago
Low-power bus encoding using an adaptive hybrid algorithm
In this paper, we propose an adaptive low-power bus encoding algorithm based on weighted code mapping (WCM) and the delayed bus technique. The WCM algorithm transforms an original...
Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru...