Sciweavers

517 search results - page 86 / 104
» The design of a low energy FPGA
Sort
View
DAC
2012
ACM
11 years 9 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
MOBIQUITOUS
2007
IEEE
14 years 1 months ago
Battery-Aware Embedded GPS Receiver Node
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
Dejan Raskovic, David Giessel
MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
14 years 1 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha
ISCA
2007
IEEE
168views Hardware» more  ISCA 2007»
14 years 1 months ago
Limiting the power consumption of main memory
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...
Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Me...
SENSYS
2003
ACM
14 years 17 days ago
CODA: congestion detection and avoidance in sensor networks
Event-driven sensor networks operate under an idle or light load and then suddenly become active in response to a detected or monitored event. The transport of event impulses is l...
Chieh-Yih Wan, Shane B. Eisenman, Andrew T. Campbe...