72 search results - page 12 / 15 » The design of a low power asynchronous multiplier |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
TVLSI
2010
13 years 2 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
25
Voted
IPPS
2003
IEEE
14 years 24 days ago
2003
IEEE
Clustering is an important characteristic of most sensor applications. In this paper we define COSMOS, the Cluster-based, heterOgeneouS MOdel for Sensor networks. The model assum...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
ISLPED
2009
ACM
14 years 6 days ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...