Sciweavers

979 search results - page 159 / 196
» The dynamic granularity memory system
Sort
View
FPGA
2005
ACM
97views FPGA» more  FPGA 2005»
14 years 3 months ago
Techniques for synthesizing binaries to an advanced register/memory structure
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
LCTRTS
2007
Springer
14 years 4 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
CGO
2006
IEEE
14 years 4 months ago
Thread-Shared Software Code Caches
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
Derek Bruening, Vladimir Kiriansky, Timothy Garnet...
ISCA
2008
IEEE
185views Hardware» more  ISCA 2008»
13 years 10 months ago
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware
Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely...
Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chu...
IPPS
2008
IEEE
14 years 4 months ago
Performance comparison of SGI Altix 4700 and SGI Altix 3700 Bx2
Suitability of the next generation of high-performance computing systems for petascale simulations will depend on a balance between factors such as processor performance, memory p...
Subhash Saini, Dennis C. Jespersen, Dale Talcott, ...