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PDP
2008
IEEE
14 years 4 months ago
Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
Gregorio Quintana-Ortí, Enrique S. Quintana...
CODES
2007
IEEE
14 years 4 months ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 4 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
FGCN
2007
IEEE
109views Communications» more  FGCN 2007»
14 years 4 months ago
Flow Balancing Hardware for Parallel TCP Streams on Long Fat Pipe Network
Parallel TCP streams are used for data transfer between clusters in today's high performance applications. When parallel TCP streams are used on LFN, part of streams fail to ...
Yutaka Sugawara, Mary Inaba, Kei Hiraki
ICC
2007
IEEE
145views Communications» more  ICC 2007»
14 years 4 months ago
Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm
Low-density parity-check codes using the beliefpropagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical stru...
Zhiyong He, Sébastien Roy 0002, Paul Fortie...