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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 2 months ago
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
Se-Hyun Yang, Babak Falsafi
AAAI
2006
13 years 10 months ago
Reinforcement Learning with Human Teachers: Evidence of Feedback and Guidance with Implications for Learning Performance
As robots become a mass consumer product, they will need to learn new skills by interacting with typical human users. Past approaches have adapted reinforcement learning (RL) to a...
Andrea Lockerd Thomaz, Cynthia Breazeal
ISCA
1998
IEEE
143views Hardware» more  ISCA 1998»
14 years 1 months ago
Lockup-Free Instruction Fetch/Prefetch Cache Organization
In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probabili...
David Kroft
MOBIHOC
2009
ACM
14 years 9 months ago
Predict and relay: an efficient routing in disruption-tolerant networks
Routing is one of the most challenging open problems in disruption-tolerant networks (DTNs) because of the shortlived wireless connectivity environment. To deal with this issue, r...
Quan Yuan, Ionut Cardei, Jie Wu
ICPP
2008
IEEE
14 years 3 months ago
Machine Learning Models to Predict Performance of Computer System Design Alternatives
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
Berkin Özisikyilmaz, Gokhan Memik, Alok N. Ch...