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KDD
2005
ACM
92views Data Mining» more  KDD 2005»
16 years 3 months ago
Summarizing itemset patterns: a profile-based approach
Frequent-pattern mining has been studied extensively on scalable methods for mining various kinds of patterns including itemsets, sequences, and graphs. However, the bottleneck of...
Xifeng Yan, Hong Cheng, Jiawei Han, Dong Xin
VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
16 years 3 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
98
Voted
HPCA
2005
IEEE
16 years 3 months ago
Distributing the Frontend for Temperature Reduction
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
Antonio González, Grigorios Magklis, Jos&ea...
RECOMB
2001
Springer
16 years 3 months ago
Geometric algorithms for the analysis of 2D-electrophoresis gels
In proteomics 2?dimensional gel electrophoresis (2?DE) is a separation technique for proteins. The resulting protein spots can be identified by either using picking robots and sub...
Alon Efrat, Frank Hoffmann, Klaus Kriegel, Christo...
ICCAD
2001
IEEE
126views Hardware» more  ICCAD 2001»
16 years 9 days ago
Constraint Satisfaction for Relative Location Assignment and Scheduling
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Je...