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VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
14 years 3 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
ARITH
2007
IEEE
14 years 4 months ago
A New Family of High.Performance Parallel Decimal Multipliers
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
Álvaro Vázquez, Elisardo Antelo, Pao...
FPL
2008
Springer
193views Hardware» more  FPL 2008»
13 years 11 months ago
Decimal multiplier on FPGA using embedded binary multipliers
Horácio C. Neto, Mário P. Vés...