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» The logic of bunched implications
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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 4 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
ICCAD
2001
IEEE
84views Hardware» more  ICCAD 2001»
14 years 4 months ago
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...
Seiji Kajihara, Kohei Miyase
IPPS
2008
IEEE
14 years 2 months ago
Exploiting spatial parallelism in Ethernet-based cluster interconnects
In this work we examine the implications of building a single logical link out of multiple physical links. We use MultiEdge [12] to examine the throughput-CPU utilization tradeoff...
Stavros Passas, George Kotsis, Sven Karlsson, Ange...
SP
2006
IEEE
110views Security Privacy» more  SP 2006»
14 years 1 months ago
Privacy and Contextual Integrity: Framework and Applications
Contextual integrity is a conceptual framework for understanding privacy expectations and their implications developed in the literature on law, public policy, and political philo...
Adam Barth, Anupam Datta, John C. Mitchell, Helen ...
LACL
2001
Springer
14 years 1 days ago
On the Distinction between Model-Theoretic and Generative-Enumerative Syntactic Frameworks
Abstract. Two kinds of framework for stating grammars of natural languages emerged during the 20th century. Here we call them generativeenumerative syntax (GES) and model-theoretic...
Geoffrey K. Pullum, Barbara C. Scholz