295 search results - page 7 / 59 » The rendering architecture of the DN10000VS |
ACSC
2005
IEEE
14 years 1 months ago
2005
IEEE
The Address Recalculation Pipeline is a hardware architecture designed to reduce the end-to-end latency suffered by immersive Head Mounted Display virtual reality systems. A deman...
Publication
Continuing improvements in CPU and GPU performances as well as increasing multi-core processor and cluster-based parallelism demand for flexible and scalable parallel rendering sol...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This paper presents a method of using texture mapping with mipmapping to render a VLSI layout. Texture mapping is used to save already rasterized areas of the layout from frame to...
MM
2000
ACM
13 years 11 months ago
2000
ACM
We present a new approach for faster rendering of large synthetic environments using video-based representations. We decompose the large environment into cells and pre-compute vid...
VISUALIZATION
2005
IEEE
14 years 28 days ago
2005
IEEE
In this work we present a hardware-accelerated direct volume rendering system for visualizing multivariate wave functions in semiconducting quantum dot (QD) simulations. The simul...