98 search results - page 3 / 20 » The scaling of interconnect buffer needs |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
1 We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of timetriggered and event-triggered clusters, interc...
19
Voted
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
SIGMETRICS
1990
ACM
13 years 11 months ago
1990
ACM
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
AICT
2009
IEEE
14 years 19 days ago
2009
IEEE
Multilayer MINs have emerged mainly due to the increased need for routing capacity in the presence of multicast and broadcast traffic, their performance prediction and evaluation ...