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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 11 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ICCAD
1997
IEEE
129views Hardware» more  ICCAD 1997»
13 years 11 months ago
A fast and robust exact algorithm for face embedding
We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all fac...
Evguenii I. Goldberg, Tiziano Villa, Robert K. Bra...
DAC
1997
ACM
13 years 11 months ago
Wire Segmenting for Improved Buffer Insertion
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...
Charles J. Alpert, Anirudh Devgan
GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
13 years 11 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
ICCAD
1994
IEEE
114views Hardware» more  ICCAD 1994»
13 years 11 months ago
Performance-driven synthesis of asynchronous controllers
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...