145 search results - page 10 / 29 » The use of random simulation in formal verification |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulatio...
COMPSEC
2010
13 years 4 months ago
2010
Spi Calculus is an untyped high level modeling language for security protocols, used for formal protocols specification and verification. In this paper, a type system for the Spi ...
ESM
2000
13 years 9 months ago
2000
The framework of this paper is the design of complex communication protocols by simulation, based on formal description techniques (FDT). We propose a general-purpose scalable mod...