145 search results - page 11 / 29 » The use of random simulation in formal verification |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
PTS
2010
13 years 5 months ago
2010
We present a novel algorithm for test data generation that is based on techniques used in formal software verification. Prominent examples of such formal techniques are symbolic ex...
PDSE
1998
13 years 9 months ago
1998
The development of correct OO distributed software is a daunting task as soon as the distributed interactions are not trivial. This is due to the inherent complexity of distribute...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
MICRO
2008
IEEE
13 years 7 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...