145 search results - page 2 / 29 » The use of random simulation in formal verification |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
tive Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu Department of Computer Science, University of British Columbia, {depaulfm, ajh}@cs.ubc.ca D...
ITC
2003
IEEE
14 years 26 days ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
CAV
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
CAV
1990
Springer
13 years 11 months ago
1990
Springer
Ternary system modeling involves extending the traditional set of binary values