Sciweavers

145 search results - page 8 / 29
» The use of random simulation in formal verification
Sort
View
IFIP
2001
Springer
14 years 3 days ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
HVC
2007
Springer
153views Hardware» more  HVC 2007»
13 years 11 months ago
On the Architecture of System Verification Environments
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
Mark A. Hillebrand, Wolfgang J. Paul
CODES
2005
IEEE
14 years 1 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
13 years 9 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
AGTIVE
2007
Springer
13 years 11 months ago
Visualization, Simulation and Analysis of Reconfigurable Systems
Meta-modeling is well known to define the basic concepts of domain-specific languages in an object-oriented way. Based on graph transformation, an abstract meta-model may be enhanc...
Claudia Ermel, Karsten Ehrig