26 search results - page 5 / 6 » Thermal via placement in 3D ICs |
VLSID
2010
IEEE
13 years 5 months ago
2010
IEEE
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...
ISPD
2011
ACM
12 years 9 months ago
2011
ACM
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
ICCAD
2007
IEEE
14 years 3 months ago
2007
IEEE
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
DAC
2011
ACM
12 years 6 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...