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» Thermal-Aware 3D IC Placement Via Transformation
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DAC
2011
ACM
12 years 7 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
ASPDAC
2008
ACM
107views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Full-chip thermal analysis for the early design stage via generalized integral transforms
The capability of predicting the temperature profile is critically important for timing estimation, leakage reduction, power estimation, hotspot avoidance and reliability concerns ...
Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee
ICCAD
2010
IEEE
216views Hardware» more  ICCAD 2010»
13 years 5 months ago
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Through-silicon via (TSV) fabrication causes tensile stress around TSVs which results in significant carrier mobility variation in the devices in their neighborhood. Keep-out zone ...
Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok...
ECCV
2010
Springer
13 years 9 months ago
Extrinsic camera calibration using multiple reflections
Abstract. This paper presents a method for determining the six-degreeof-freedom (DOF) transformation between a camera and a base frame of interest, while concurrently estimating th...
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
14 years 4 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...