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HPCA
2007
IEEE
14 years 7 months ago
Illustrative Design Space Studies with Microarchitectural Regression Models
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
Benjamin C. Lee, David M. Brooks
CASES
2007
ACM
13 years 11 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
MICRO
2000
IEEE
61views Hardware» more  MICRO 2000»
13 years 11 months ago
Reducing wire delay penalty through value prediction
In this work we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating...
Joan-Manuel Parcerisa, Antonio González
HPCA
2000
IEEE
13 years 11 months ago
Dynamic Cluster Assignment Mechanisms
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
IJHPCN
2008
94views more  IJHPCN 2008»
13 years 7 months ago
Analysing and improving clustering based sampling for microprocessor simulation
: We propose a set of statistical metrics for making a comprehensive, fair, and insightful evaluation of features, clustering algorithms, and distance measures in representative sa...
Yue Luo, Ajay Joshi, Aashish Phansalkar, Lizy Kuri...