Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel