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IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
14 years 3 months ago
The positive effect on IC yield of embedded Fault Tolerance for SEUs
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
André K. Nieuwland, Richard P. Kleihorst
DAC
2003
ACM
14 years 3 months ago
Test application time and volume compression through seed overlapping
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
14 years 3 months ago
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
14 years 3 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
14 years 3 months ago
Understanding and minimizing ground bounce during mode transition of power gating structures
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel