The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy ...
Brandon Rumberg, David W. Graham, Vinod Kulathuman...